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ASAHI KASEI
[AK2358AI
i
Features
*1 *1 *1 *1 *1 *1
1
u
*1 *1
u
*1
u
*1 *1
u
*1 *1
u
Built-in voice filter for cordless telephone, MSK MODEM (2400bps), COMPANDOR, and scrambler circuit Low / wide operation voltage range (1.9 V to 5. 5V) Built-in COMPANDOR output transient response circuit and time constant circuit No external component is needed for COMPANDOR Built-in buffer amplifier for ceramic receiver driving. Built-in electronic volume for u icrophone sensitivity and modulator/demodulator sensitivity Receiving level switchable in 8 steps (-12 to +9dB) Built-in muting function for voice transmitting and receiving External adjustment for the limiter levelBuilt-in amplifier for transmission and reception gain adjustment Low power CMOS and power-down function Built-in 3.58MHz oscillator circuit Scrambler circuit with frequency inversion. Two inversion frequencies can be selected. Bypassing the scrambler circuit available Built-in frame detection function for the MSK demodulator Control register and MSK MODEM data buffer controlled by serial interface Few external component is necessary resulting cost reduction and small set size. Package: 24 pin VSOP
1
microphone input
Block
Diagram
I
Transmission signal output
T% D a t a / l x D a t a Control data
3. 58MEz
frase d e t e c t i o n Receptlnn s i g n a l Receiver Input
Recept 100 o u t p u t
0151 E-00 -1
1996 12
0
ul m o
M
.
A I
T .
4
I
5
I
I
3:
.......................
TXHPF +VR1 Compressor A
T
TXAFSW Scrambler ~ Limiter ~zl!v
.................... TDATA TCLK DIR SCLK D1/O RDF/FD
N
4
9 --1- ~~~~a~isj ~ TC IISK _ Modulator v IISK Demodulator 1 IISKHPF
9
~ data buffer ~
--
v
BUFON
0
"
~
.............. `r
""~ I I
DeRXAFSW
p# emphasis
44 De~ Scrambler
:., . . . . . . . . . . . Re eiver 2 L BUFOP
J
RECSW , . . . . . . . . . . . . . . . . . *:-j \AMp3 j `3 . . . . . . . . . . . . %
VR4
"J& Expander 4
I +
RXHPF
e
hJ22..j
n >
co w
Operating mode
E
cd
N3
m a.
ASAHI KASEI
[AK2358AI Description I
1
The AK2358A, a base-band LSI for cordless telephone, has built-in voice filters, a 2400bps MSK MODEM for data communication, a frame detection circuit, a COMPANDOR for noise reduction, and scrambler circuits. The CMOS process provides low power operation. Application of 24 pin VSOP package with the feature of significant reduction of external component provides minimum mounting area. The time constant circuit for the COhlPANDOR output transient response is built into the LSI. Using a 2400bps MSK MODEM for data communication has realized high data reliability and high speed communication at the same time. This LSI is suitable for cordless system telephones etc. which requires complicated protocol control. An oscillation circuit with a 3.58MHz crystal oscillator is built in, and no other frequency source is required for the MSK MODEM. The oscillator also can be used for the other DTMF generator etc. The scrambler circuit uses the simple Inversion method with inversion of the voice spectrum around the carrier frequency. Two inversion frequencies can be selected. Built-in electronic volumes provided for transmission and reception part realize automatic adjustment of the u icrophone sensitivity and the modulator/demodulator sensitivity by external EEPROM and u icroprocessor. The transmission part is composed of high-pass filter, compressor, pre-emphasis circuit, scrambler, limiter, MSK modulator, splatter filter, electronic volume control, etc. The reception part is composed of band pass filter, de-emphasis circuit, de-scrambler, expander, buffer amplifier, MSK demodulator, frame detection circuit, electronic volume control, etc.
s Pin Arrangement
24 pin VSOP
AGNDINC TAGNDC TXINC TXINOC LIMLVC MODC Vssc TCLKC TDATA~ DI/Oc RDF/FDc SCLK c
lo 2 3 4 5 6 7 8 9
2 4 3 RAGND 2 3 -J RXIN 2 2 -J RXINO 21 ~ BUFOP 20 --J BUFON 19 -J RXAF 18 3 RXAFIN 17 3 EXPOUT 16 3 VDD 15 3 XIN 14 3
10
11 12
XOUT
13 ~DIR
0151 E 00
1996 12
ASAHI KASEI
[
[AK2358AI Circuit Configuration I
Block AMP1
TXHPF Compressor Pre-emphasis
Scrambler (Tx)
Limiter
Splatter filter
MSK modulator AMP2
RXLPF
RXHPF De-emphasis De scrambler (Rx)
Function The operational amplifier for voice signal transmission gain adjustment and for the filter to eliminate aliasing noise by the SCF(switched capacitor filter) in the following stage. Use an external resistor and capacitor to set the gain less than 30dB and the cut-off frequency to about 10kHz. The SCF circuit to eliminate the low frequency component less than 300Hz from the transmission voice signal. The circuit to compress the amplitude of the transmission voice signal. The circuit to emphasis the high-frequency component of the transmission voice signal to improve the S/N of the modulation signal. The circuit to inverse the transmission voice spectrum in regard to the carrier frequency. Carrier frequency can be selected from two frequencies by KEY. PCONT select to use the scrambler or the pre-emphasis circuit. The amplitude-limiting circuit to suppress the frequency deviation of the modulation signal. The limitation level can be adjusted by applying a DC voltage to the LIMLV pin. If the LIMLV pin is open, the default limitation level is applied. The SCF circuit to eliminate the high frequency component higher than 3kHz from the limiter output signal or the MSK modulator signal. The circuit to generate a 2400bps MSK signal according to the received digital signal logic from the TDATA pin. The operational amplifier to adjust the reception demodulation signal gain and for the filter to eliminate the aliasing noise of the SCF in the following stage. Set the gain to less than 30dB and the cut-off frequency to about 10kHz by external resister and capacitor. The SCF circuit to eliminate the high frequency component higher than 3kHz from the limiter output signal or the MSK modulator signal. The SCF circuit to eliminate the low frequency component lower than 300Hz from the reception voice signal. The circuit to de-emphasis the emphasized signal by pre-emphasis circuit. The circuit to re- inverse the spectrum of the scrambled receiving voice signal respect to the carrier frequency. Carrier frequency can be selected from two candidates by a KEY. The de-scrambler(Rx) or the de-emphasis circuit can be selected by PCONT. The circuit to expand the signal amplitude compressed by the compressor.
Expander
0151 Eoo
4-
1996/'12
ASAHI KASEI Block AMP3
[AK2358AI
7
r
AGND
P
VR2 VR3
Oscillation circuit VR1
r
VR4 Control register and data buffer
Function The operational amplifier used on the smoothing filter of the reception SCF output. Set the gain to OdB and the cut-off frequency to about 20kHz by external resister and capacitor. The SCF circuit to eliminate the low frequency component lower than 100Hz from the reception MSK signal. The circuit to reproduce the 2400bps receiving data and the clock from the received MSK signal in the RXIN pin. The inverting and the non-inverting buffer amplifier to drive the ceramic receiver. The circuit to generate the reference voltage for the internal analog signal. The circuit to oscillate the 3.58 MHz reference clock using an external crystal oscillator and resistor. The volume to control the input amplitude of the transmission voice signal. The adjustment range is -8dB to +7dB by ldB step. The volume to control the MOD output amplitude. The adjustment range is -4dB to +3.5dB by 0.5dB step. The volume to control the input amplitude of the reception demodulation signal. The adjustment range is -4dB to +3.5dB by 0.5dB step. The volume to control the receiving voice amplitude. The adjustment range is -12dB to +9dB by 3dB step. The control register contlols the status of internal switches and internal volumes of the LSI by serial data consists of 2 address bits and 8 data bits. At the start up a power-on-reset circuit works and the default values are set to the control register.
(see control register map.)
The data buffer stores 8 bits of the MSK receiving data to smooth the signal interface with CPU. Pin/Function
1/0
I
I
Pin No. 1
Pin name ACNDIN
I
2
TAGND
o
3
TXIN
I
4 5
TXINO LIMLV
o
I
Function Analog ground input pin. Connect the capacitor to stabilize the analog ground. Analog ground pin for the transmission system. Connect the capacitor to stabilize the analog ground. Transmission voice input pin. This is the inverting input pin for AMP1. It composes a microphone amplifier with a ex~ernal resister and a capacitor. .4i111 output pin. Limitation level adjustment pin. The limitation level can be adjusted by applying a I)C vollagc' to this pin. The default limitation level is adopted if no voltage is applied.
0151 "E-00
1996 12
ASAHI KASEI Pin No. 6 7 8 Pin nane
MOD Vss
[AK2358AI 1/0
o -- o
TCLK
9
TDATA
I
10
11
DI/O RFD/FD
1/0
o
12 13 14
SCLK DIR XOUT
I I I
15 16 17 18
X?N VDD EXPOUT RXAFIN
o
-- I
o
19
RXAF
o
20
BUFON
21 22 23
BUFOP
RXINO
o o o
RXIN
I
24
RAGND
o
Function Output pin of the modulated transmission signal. A load impedance larger than 10kQ can be driven. Negative power supply pin. Clock output pin for the MSK data transmission. A 2.4kHz clock is put out by setting the internal register TDE to "O". If the register is set to "l", it goes "H" level. MSK transmission data input pin. Data are latched synchronizing with the TCLK rising edge. Serial data input and output pin. MSK signal reception flag output and Frame detection signal output pin. This pin puts out two types of information, depending on the status of the internal register FSL. If FSL is "l", it is MSK signal reception mode, so the pin reaches low after 8 bits of the MSK reception signal have been written to the data register. If FSL is "O", it is the frame detection signal output mode, so the low pulse is put out after a frame pattern is detected. Clock input pin for serial data 1/0. Serial data 1/0 control pin. Crystal oscillator connection pin. The reference clock IC is generated by connecting a 3.58MHz crystal oscillator parallel to a lMQ resistor between this pin and XIN pin. In case of external clock operation, connect XOUT pin to YSS and apply the clock to XIN. Crystal oscillator connection pin. Positive power supply pin. Expander output pin. Reception voice input pin. This is the inverting input of AMP3. It composes a smoothing filter by external resistor and capacitor. Reception voice output pin. This is the output pin of AMP3. A load impedance more than 10kQ can be driven. Receiver amplifier output pins. Connect the ceramic receiver between these two pins. f\MP2 output pin. Demodulated receiving signal input pin. This is the inverting input of AMP2. It composes a prefilter with external resistor and capacitor. \nalog ground pin for the reception system. Connecl the capacitor to stabilize analog ground.
0151 E 00 6
1996:12
ASAHI KASEI I VSS=OV; Note 1) Parameter Power supply voltage: (VDD) Input current (except the power supply pins) Analog input voltage Digital input voltage Storage temperature Symbol VA+
IIN
[AK2358AI Absolute Maximum Ratings 1 max
6.5
tlo
min
"0.3
Unit
v
mA
v
VINA
-0.3
(VA+)+O.3
V,N~ Tstg
-0.3 -55
(VA+)+O. 3 130
v "c
Note 1): All voltages with respect to the VSS pin. Warning: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
I
Recommended VSS=OV; Note 1) Parameter Operation temperature Power supply voltage: (VDD) Analog reference voltage Current consumption Mode O Mode 1 Mode 2 Mode 3
Operating
Conditions
I Unit
"c
Symbol Ta VD+ AGND IddO Iddl Idd2 Idd3
min -lo 1.9
typ 2.0 l/2VD+
0.1
max
70
5.5 0.8 1.9 2.9 10
v
v
mA
0.9 1.4 5.5
Note 1): All voltages with respect to the VSS pin.
0151-E-00 -7
1996 12
ASAHI KASEI
1
[AK2358AI
Analog
Characteristic
s
I
f=lkHz, PCONT="l", TC="l", EM="l", VR1 to VR4=OdB: unless otherwise specified, OdBm=O.775Vrms OdBx=-5dBm at AVDD=2V Note 8) 1) TX system Parameter Standard input level @TXINO Absolute gain TXINO-MOD Note 1) Limiter level JiOD lkHz Note 1) No external R Adjustment range by external R Compressor linearity TXINO-MOD Note 1) 2) TXINO=-44dBx I TXINO=-50dBx Noise without input TXINO~MOD Note 1) 3) Compressor distortion TXINO+MOD TXINO=-10dBx Transmission MSK @MOD Note 1) signal level 1.2kHz signal output Transmission MSK @MOD Note 1) signal distortion 1.2kHz signal output 2) RX system Parameter Standard input level @RXINO Absolute gain RXINO-BUFON,BUFOP Note 1) RXINO-BUFON,BUFOP Expander linearity Note 1) 4) RXINO=-25dBx RXINO=-30dBx RXINO-BUFON,BUFOP Noise with no input Note 1) 3 ) Expander distortion RXINO+RXAF RXINO=-5dBx Reception MSK @RXINO signal level 1.2kHz signal output min -1.5 typ -lo
0
max I
min 2.0 -4.5
typ
-lo
max 5.0 -2.5 -2.5
3.5 -3.5
Unit dBx dB dBx
I
-20 -24
]
-17.0
-20.0
I
-14 -16 -36.5 -35
I dB dBm dB dBx dB
-4.5
-3.5
-2.5 -32
Unit dBx dB
+1.5
-33.0 -45.0
-30.0 "40. o
-27.0
-35.0 -70 -35
dB dBm dB dBx
-14
-7
-1
0151-E-00 -8
1996 12
ASAHI KASEI 3) Overall characteristics Parameter Absolute gain TXINO~BUFON, BUFOP Note 5) TXINO=-10dBx KEY="O" or "1" TXINO~BUFON, BUFOP Note 3) 5) Distortion TXINO=-10dBx KEY="O" or "l" Crosstalk @BUFON,BUFOP Note 1) Transmission ~ Reception TC="O" TXINO=OdBx @MOD Crosstalk Note 1) Reception ~ Transmission T.~=?*(j. RXINO=OdBx 4) Filter characteristics Parameter Transmission overall characteristics (See Fig.1) TXINO ~ MOD 100Hz TC=" O" EM="l" PCONT="l" 300Hz Relative value with OdB gain 2. 5kHz a t lkHz 3kHz 5kHz Reception overall characteristics (See Fig.2) RXINO ~ EXPOUT 100Hz TC=" O" EM="l" PCONT="l" 250Hz Relative value with OdB gain 300Hz a t lkHz 3kHz 5kHz min typ max
-40 -9 9.5
[AK2358AI
min 6) 6) 7)
o
typ
max
+4. o
Unit dB dB
-50
-43
-60
dBx
7) -56.5 dBx
Unit
-12 6.5 6.5
-10.5
8 8
dB
9.5 -7 -4 13.5 dB -7.5 -15
9
-10.5
12 10.5 -9
Note 1) With the external circuit shown in the application circuit example. Note 2) Relative value with OdB as the MOD output level at the time of input of standard input level (-10dBx) to TXINO. Note 3) With the C-message filter. Note 4) Relative value with OdB as the BUFON, BUFOP output level at the time of input of standard input level (-10dBx) to RXINO. Note 5) With the external circuit shown in the application circuit example. Further, the AhlP2 gain should be -3.5dB, and MOD and RXIN should be in loop connection. Note 6) TC=,T,$$, PCONT="O" Note 7) ~c=~,()*~, PCONT="O" Note 8) The dBx is standardized unit valid for various power supply voltages from 1.9 to 5.5V. If the voltage is 2V, OdBx should be -5dBm. With the other voltage as X iV], O d B x z -5 + 20 log (X2) [dBm].
0151-E 00
1996 12
ASAHI KASEI *l Filter characteristics
GA IN(dB)
[AK2358AI
10 0 -lo
-20 -30 -40 -50
10
FREQUENCY
-
Fig. 1
Transmission overall characteristics
10
0
-lo
-20 -30 -40
-50
/
,01 I ,02 ,03
I
,04
FREQUENCY
Fig. 2
Reception overall characteristics
ICI
"
ASAHI KASEI
[
[AK2358AI
Level
Diagram
I
1) TX system
UK
klodul ator f-lkHz TXAF Pref i I ter (AUP1) OS30dB TXINO
~
Cross point -lOdBx
MOD
H~ddE3+w:i.H AUP j-=
Limiter level -ldh 0:: "~dB +3.5dB .Scraable
O:jdB
.................... ............... ........ ....... ................
-3. SdBx(USKs19nsl level) $.5 -6.3dBx(referencs level) ..................
14 ...............
-23.5dBx -Z6.sdnx
. . . . . . . . . . . . . . . . . . . . ., ................... ...................... .................... ...................... .....................
2) RX system
f-1 kHz RXINO EXPOUT RXAF
`"~PJ:'Ho:~dBH'''4''"r='c:'
-b.&t-
dBx
10 0 -10 -23 -25 -20 -4, / -45 j / -50 / . ~~ .... . . .
I
-44d0x
I
Note) The dtlx is standardized unit valid for various power supply voltages from 1.9 to 5.5V. [f lhe voltage is 2V, OdBx should be 5dBm. With the other voltage as X [V], OdBx 5 ~ 20 log (X/2) [dBml.
I
" "'""
0151-E 00 11 "
1996/'12
ASAHI KASEI
I
[AK2358AI
Diz ital
Characteristic
s
I
1 . DC Characteristics
I
Parameter I High-level input voltage 1 Low-level input voltage 1 Hi~h-level inuut voltage 2 Low-level input voltage 2 V1"'VD+ High-level input current Low-level input current V,,'ov Hizh-level outDut Voltaze I.H'O. lIIIA l Low-level outDut voltage 1~,
Pin ]Svmbol] min I tvu I max I Unit I v I 70%VD+ I (1) ~lH I 30%VD+ / v (1) VIL vI I 80!%VDti I (2) VIH v 20%VD+ (2) VIL 10 PA (l)(2) IIH PA -lo (l)(2) IIL 90%VD+ v (3) v(-). I I 0.3 I v I =0.6mAl (3) I Vfi, I
(l). TDATA. DI/O (2) SCLK, DIR (3) TCLK, RDF, DI/O
2. AC Characteristics Parameter Master clock frequency MSK modulator timing TDE Falling to TCLK Rising TCLK period TDE Rising to TXAFSW Falling TDATA Set up time TDATA Hold time TDATA Hold time2 MSK demodulator timing RCLK Period & FD pulse width Serial data input timing Clock pulse width 1 Clock pulse width 2 SDATA Set Up time SDATA Hold time DIR Set up time DIR Hold time DIR falling to SCLK falling time SCLK;DIR input rising time SCLK;DIR input falling time RDF falling to SCLK falling time SCLK rising to RDF falling time I Svmbol I f;lk T1 T2 T3 TS TH TH2 T ta tb tc td te tf tg th ti tj tk u in
I
tvr) I 3.579545 208.3 416.7
!
max
I Unit MHz ps ps ms /us /ls ,LLS fis ns ns ns ns ns ns ns
2 1 1 2 402.2 500
500
416.7
100
100 100 100 100 1 1 100 600
/L S jl S
ns ns
0151-E 00 12
199612
[AK2358AI
TCLK TX AFSW Note) ( Internal registsr ) TDE Note) ( I n t e r n a l rsgister ) I'DATA MOD
I ~~ ~
I
I
I
::
Voice signal MSK modulator
Voice signal
:
<
ta
:tb: ,, ,:. : llJ1 . . . . . . . . . . . . . . . ..~ Ao .................. Dl $0 ~
SCLK DI/O
;.
-~: -1
DIR
~"""""""""""""""" i :tg~ w
:.....-.0. 8DVDD
SCLK/DIR input Note) The timing to rewrite the internal registers TXAFSW and TDE is synchronized with the falling edge of DIR.
o151-f"oo -13-
.
) 1
\
1 1
1
C'4 :
1+ . .
1
: .
n m.
s . . : : . > ,. . :* ,
--
Q
a
0
4 a n.
IA .-
*
L *
a
)
.
r
I
t-l
al
o \ a
MSK demodulator 1996/12
ASAHI KASEI
[AK2358AI Control
I
s Register composition
Register
Map
I
Address A l AO Control register 1 Volume register Volume register Control register 2 + volume register Reception data register 0
o
D7 FSL 1 TC
D6 BS2 1
D5 BS 1 1
D4 FCLN 1 KEY
Data D3 PCONT RECSW
D2 TDE
0
1 0
D1 DO TXAF RXAF
"SW `SW
1 1
VR2 EM FRPT
VR4 VR1 VR3
1
MSK MODEM reception data
The-reception data register is a read only register, and the others are write only registers. The reception data register has no address information proceeding to the Data. Set the all bits D4 to D7 of volume register address "01" to "l". If they are set to "O", it changed to test mode,
s Register map 1) Control register 1 Address Al AO
o 0
Data D7 FSL 1 D6 BS2 1 D5 BS1 D4 FCLN D3 PCONT
(Default)
0
0
1
D2 TDE 1
D1 TXAFSW
DO RXAFSW
0
0
a) Transmission signal control TDE 1 1
o
TXAFSW
0
1
1
Transmission output Voice signal Mute MSK signal
b) Reception signal control
RXAFSW 1
o o
RECSW -- 1
0
RXAF Mute ON
ON
I BUFOP/BUFON Mute Mute
ON
c) Scrambler circuit ON/OFF I
I
PCONT 1
o
!I
!1
I
BvDass (Scrambler OFF) Scrambler works (ON) I I
I
I
0151-E-00
-15-
1996/12
AS.!HI KASEI d) Frame detection circuit ON/OFF FCLN 1 o The frame detection function is not used (OFF). The frame detection function is used (ON).
Note) FCLN automatically changes from O to 1 when a synchronized frame is detected. e) Power-down mode BS2 1 o 1 o BS1 1 1 0 0 Mode name modeO model mode2 mode3 Voice system + transmission MSK OFF OFF OFF ON Reception MSK OFF OFF ON ON Oscillator OFF ON ON ON
f) RDF/FD selection FSL 1 o The MSK signal reception flag (RDF) is put out from the RDF/FD pin. The frame detection signal (FD) is put out from the RDF/FD pin.
2) Control register 2 Address Al AO 1 1 (Default) Data name KEY FRPT EM TC Data D7 TC 1 D6 EM 1 D5 FRPT D4 KEY D3 1 I D2 I D1 I DO VR3
0
1
0
0
0
Function Carrier inverting frequency " 1 ": 3.107kHz "O": 3.290kHz Frame detector detection pattern "l": 1100010011010110 (base unit) "O": 1001001100110110 (portable unit) Emphasis circuit " 1 ": Passage (ON) "O": Bypass (OFF) COMPANDOR circuit "l": Passage (ON)
3) Volume register Address A l AO o 1 1 0 1 1 Data D7 1 VR23 TC D6 1 VR22 EM D5 1 \'R21 FRPT D4 1 VR20 KEY D3 RECSW VR13 VR33 D2 VR42 VR12 VR32 D1 VR41 VR1l VR31 DO VR40 VR1O VR30
0151-E 00 16 -
1996/12
ASAHI KASEI a ) VR1 volume control VR13 o 0 0 0 0 0 o 0 1 1 1 1 1 1 1 1 VR12 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VR1l 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VRIO 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Volume gain (dB) -8. O -7. o -6. O -5. o -4. o -3.0 -2. o -1.0 0 +1.0 +2. o +3.0 +4. o +5. o +6. O +7. o
[AK2358AI
b) VR2, VR3 volume control
VR23 VR33 o 0 o 0 o o o o 1 1 1 1 1 1 1 1
VR22 VR32 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
VR21 VR31 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
VR20 VR30 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Volume gain (dB) -4. o -3.5 -3. o -2.5 -2.0 -1.5 -1.0 -o. 5 0 +0.5 +1.0 +1.5 +2.0 +2.5 +3.0 +3.5
0151 -EOO 17
-
1996i12
ASAHI KASEI c) VR4 volume contro
[AK2358AI
I
T242
o o o
VR41
0 0
I
VR40
0
1
Volume ~ain (dB)
-12
I
1
0
o 1 1 1 1
1 1 0 0 1 1
1 0 1 0 1
-9 -6 -3 0 +3 +6 +9
Note) By reset, the gain of all volumes are set to OdB and RECSW bit is changed to "o". 4) MSK MODEM reception data Data D7 RD7 Data name RDO t RD7 D6 RD6 D5 RD5 D4 RD4 D3 RD3 D2 RD2 D1 RD1 Function "1":1.2kHz "0":2.4kHz DO RDO
MSK reception data RD7 is the first received data.
0151 E-00
18
ASAHI KASEI I
MSK signal transmission flow MSK signal transmission
[AK2358AI MSK Modem i
TDE="O" and TXAFSW="l" a r e s e t .
:
MSK
transmission start
I
MSK transmission data are transmitted synchronized to TCLK.
: During MSK transmission
N
Transmission of the
TDE= "1"
: MSK data transm ssion comp etion
I
TXAFSW= "O"
I
: Switching to voice signal
(1) Set the serial register "TDE" to "O" and "TXAFSW" to "l", so that ilSK transmission state is provided. (2) A 2400Hz clock is put out from TCLK. Synchronizing with lhe rising edge of TCLK, AK2358A reads the MSK transmission data from TDATA pin and put out them to MOD pin. (3) After the transmission of the necessary number of signal bit, "TDE" of the serial . register is set to "l". (4) f\fterwards, before switcl ing to a voice signal transmission mode, wait at least 2ms after "TDE" has set to " " to complete the MSK signal final bit transm ssion. Then set TX}\FSW register to "o". 0151-E-00
-19" 1996'12
ASAHI KASEI
MSK Signal Reception
USK signal reception Y
[AK2358AI
I
FSL set to "O". : Set so that a frame detection signal (FD) is put out from the RDF/FD pin.
r
N
>
: Synchronization frame detection?
: Reception voice mute
: Set so that an USK signal reception flag (RDF) is put out from the RDF/FD pin.
N
: Reception of 8 bit of data?
Reception data read i ng I
: Reading of 8 bit of data, change to ROF/FD= "H"
: Waiting for the next synchronization frame
(1) If the internal register "FCLN" is "O", the internal nodes RDATA, RCLK are fixed to ( 2 ) After a synchronization frame is detected, FD goes to "L" during the period "T", then (3) RDATA and RCLK put out the data following to the synchronized frame pattern, and these (4) After 8 bit of reception data have been entered to the internal buffer, RDF goes "L". (5) After the CPU detect that RDF is "L", it puts out 8 clock bits to SCLK, then read 8 (6) With input of 8 clock bits to SCLK, RDF goes "H". (7) Afterwards, by repeating the steps (4) and (5) the necessary data bits are read. (8) After the necessary data have been read, DIR goes "H", "FCLN" is set to "O" via the
"1".
FCLN is set to "l".
are stored in the internal buffer.
bit of reception data from the SDATA pin.
serial interface, the internal nodes RDAT;\ and RCLK are set to "l", then the system waits for the next synchronization frame.
i
0151"E-00 -20" 1996/12
/
I
I
ASAHI KASEI
[AK2358AI Application Circuit Example I
1
ZApplication Circuit OAMP 1 Use as a transmitting microphone amplifier. The gain should be less than 30dB. To eliminate high frequency noise component over than 100kHz from input signal, 1st order or 2nd order anti-aliasing filter is necessary. The following drawing is one example of the 2nd order anti-aliasing filter, which has 30dB gain and 10kHz cut-off frequency. TXINO tJ A AblPl
<
~3 C1=2200PF
// \
. TXINR2 &
C2=33PF
cl
Rl=R2=10k L? R3=330k Q
LS1 @Smoothing filter for MOD output signal Realize low-pass filter to eliminate l12kHz clock signal component from MOD pin output signal. The following is one example of the 1st order low-pass filter which has 8.7kHz cut-off frequency. 10kQ of the modulator load resistor provide 3.3dB signal attenuation.
R
C2
R=3.9k Q
+-q
MOD
cl=4700pF C2=0. lpF RL=lOk Q
(Load resistance of MOD)
`ll
`L
0AMP2 The amplifier for the receiving gain adjustment and anti-aliasing filtering to eliminate high frequency noise component over 100kHz. The gain should be less than 30dB. The following is an example of the 2nd order low pass filter, which has 20 dB gain and 40kHz cut-off frequency. .. RXINO C1=560PF C2=27PF . AMP2
<
Rl=lOk Q R2=9. lkC? R3=100k Q LSI
0151 E 00 21 -
1996/12
ASAHI KASEI
[AK2358AI
OAMP3 The smoothing filter to eliminate 448kHz clock component from EXPOUT signal is Adding the provided by this amplifier. Also it works to adjust the receiving gain. other pass signal may be possible. The following is one example of the 1st order low-pass filter, which has OdB gain , 19kHz cut-off frequency. IEXPOUT C2 Ill
RXAFIN Cl=150pF C 2 = 0 . 0 2 2 ,uF Rl=R2=56k Q
cl
R2
RXAF @
AMP3 + LSI
+
OAGND stabilizing capacitor To stabilize the AGND potential, connect capacitors larger than 0.3LLF between TAGND pin, RAGND pin and AVSS pin. Also between AGNDIN pin and AYSS pin some capacitor is necessary to reduce the ripple of the power.
C=l #F
LSI
OVDD stabilizing capacitor To reduce the noise on VDD, connect capacitors between VDD and VSS.
VDD VDD CI-22,UF (Aluminium Electrolytic Capacitor)
cl
+
C2
C2-O.l,UF (Ceramic Capacitor)
Vss *
<
LSI
0151 E-00 22 -
1996/12
ASAHI KASEI
[AK2358AI
OCrystal oscillator - Crystal resonator , resistor and capacitors should be connected as shown Fig.3 for on-chip oscillator operation. - For external clock operation, if the high(H) level of the input clock signal amplitude equals to or is greater than 1.5V, and the low(L) level equals to or is smaller than 0.5V, then connection should be u ade as shown in Fig.4. If the input clock signal amplitude (peak-to-peak) equals to or is smaller than IV, and equals to or is greater than 200mV, then AC coupling should be as illustrated in Fig.5.
Fig.3
Fig.4
IT
XIN
O.OIPF l~External clock signal
lM Q
I XOUT
fig.5
OLimit level adjusting resistor The limiting level can be controled externally by applying DC voltage to LIMIV pin. Applied DC voltage should be larger than TAGND, then the limiting level is shown as TAGND*Va(V), while Va is the voltage between LIMIV and TAGND. Keeping LIMIV pin open provides default limit level. See following example.
VDD LIMLV R .+! L S I R=50k Q
Vss
0151 E 00 23 -
1996/12
ASAHI KASEI
[AK2358AI Package I
I
s Marking
HUHIRUNHHHH
AKM AK2358A
XXXYZ
o
UHNIIHHIIHHH
[Contents of XXXYZI
XXX: Date of manufacture Last digit of the year, week number of the year as 2 digits Y: Production lot number Z: Assembled place s Shape and dimensions of the package 24 pin VSOP
l-t%
Note:
Dimensions marked by * do not include residual res in.
(Material] Resin: Low s[ress type epoxy resin Lead frame: Cu
0151 E-00
!!P
(NN
0.1
$+
o
q'
--
_
0-10.
Detail of part A
1996/'12 24
IMPORTANT NOTICE
q These ~roducts andtheir specifications aresubject tochange without notice. Eeforeconsidering anyuseor application, consult the Asahi Kasei Microsystems Co.. Ltd. (AKMI sales office or authorized distributor concerning their current ., ,
status.
q AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of
any information contained herein.
q Any export of these products, or devices or systems containing therm, may require an export license or other official approval under the Iaw and regulations otthecountry of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
q AKM pro&cts are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device orsystem, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications ifl medicine, aerospace, nuclear energy, orotherfie[ds, in which its failure to function or perform may reasonably be expected to result in IOSS of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform May reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. . It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes Ofl or otherwise plaCeS the product with a third party to notify that paw in advanCe of the above content and conditions, and the buyer or distributor a!greeS tO aSSUflle afly and all responsibility and liability for and hold AKM harrn]ess from any and all CIaiMS ariSiflg frOlll the use of said product in the absence of such notification.

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